Engineering & Research Portfolio
18 Years.
Silicon → Systems
Package → Portfolio.
// Tony C. Chen · CFA Candidate · IC Packaging Engineer · Quantitative Researcher
從封裝工程到量化研究——同一套方法論，兩個世界的護城河 · 台灣
iPhone
3GS Package Shipped
USB-C
DP-Alt Mode Launched
Active: PCIe 5.0 Retimer
FCBGA · CoWoS · Chiplet
FEM · SPC · JEDEC Qual
CFA Candidate · Quant Backtest · R/Python
DFM · NPI · OSAT Management
AI Infrastructure · LLM Ops
00 //
The Engineering Thesis
核心論點
I started my career in 2007 doing something few engineers ever do:
drafting design rules from scratch for new substrate processes at a company that
would later become a Leading Substrate Vendor.
That first role taught me something that has defined every job since:
quality is not engineered in, it is managed in.
Over 18 years across six companies — including a Global Substrate Vendor, a Leading OSAT, and multiple Tier-1 Design Houses — I have shipped packages for
Top Smartphone Brands, launched USB 3.1 Type-C DP-Alt mode into the market,
owned RMA resolution programs for Tier-1 customers,
and built DFM process-control frameworks from the assembly floor up.
Along the way I noticed something: the statistics I used to control a plating bath
and the statistics I needed to manage a trading position were the same equations.
TonyCapm.com is where those two disciplines converge.
Statistical process control thinking applied to market drawdowns.
Process capability translated into portfolio risk budgets.
High-fidelity physics models running on proprietary infrastructure
that backtests market trend-following strategies.
This is not a pivot. It is the same system, run on a different substrate.
Tony C. Chen · CFA Candidate · Taipei, Taiwan
18 yrs semiconductor · 10+ yrs quant research
2007 – 2017 · FOUNDATION
Process & Package Engineering
Built deep substrate and IC packaging competency across a Leading Substrate Vendor, Global OSAT, and Tier-1 Design House. Shipped into Top Smartphone Brands. Launched USB3 family to market. Developed OSAT management and NPI workflows.
2017 – 2021 · EXPANSION
Customer-Facing Engineering Leadership
Moved to customer-application and quality engineering roles at multiple Tier-1 Design Houses — translating internal engineering language into customer outcomes. RMA ownership, PCN coordination, FA coordination, audit management.
2021 – PRESENT · CONVERGENCE
AI Startup + Independent Research
Package & Customer Quality Engineer at AI semiconductor startup. Working on PCIe 5.0 High-Speed Retimer assembly and process control. Simultaneously running independent quant research lab — applying semiconductor QA methodology to financial time-series data. CFA Candidate.
01 //
Career Timeline
職涯時間軸
TonyCapm · Self-Employed · Remote
Taipei, Taiwan
Quantitative Researcher
- System Architecture: Deployed scalable virtualization and sentiment pipelines. Built secure internal network tunneling across proprietary edge infrastructure.
- Algorithm Development: Engineered quant strategies. BTC Fast Trend: 48.2% annualized, Sharpe 1.85.
- Data Engineering: Adapting engineering process control methodology to financial time-series.
R · Python
Docker · Linux
SPC → Finance
Oct 2021
Apr 2025
3 yrs 7 mos
Package & Customer Quality Engineer
- Authority in assembly process control plans and DFM philosophy for High-Speed PCIe 5.0 Interface.
- Owned substrate design inputs and OSAT QMS maintenance.
- Owned end-to-end customer RMA resolution and 8D reporting.
DFM
OSAT Management
8D / CAPA
Feb 2019
Jul 2020
1 yr 6 mos
Global Semiconductor Leader
Taipei City, Taiwan
APM, Account Manager
- Coordinated Product Change Notifications (PCN) for zero-surprise transitions.
- Coordinated Failure Analysis (FA) on RMA cases for key accounts.
PCN Mgmt
Customer Quality
Jun 2017
Jan 2019
1 yr 8 mos
Tier-1 Human Interface Design House
Customer Application / IC Packaging Engineer
- Led NPI activities for automotive and consumer electronics packaging.
- Translated customer requirements into package design constraints.
NPI
Automotive Qual
Feb 2011
Jun 2017
6 yrs 5 mos
Leading USB Connectivity Design House
Package Engineer
- Launched USB 3.0/3.1, Type-C DP-Alt mode, and AOC packages.
- Led OSAT management through NPI, process control, and yield ramp.
★ Achievement: Successfully established the foundation for the Design House's USB3 packaging portfolio.
Jul 2009
Feb 2011
1 yr 8 mos
Product Engineer
★ Achievement: Introduced 8-die stack package to mass production for Tier-1 Smartphone Brand.
02 //
Proprietary Physics Study
有限元素模擬研究
⚠ SELECTED PARAMETERS REDACTED — REPRESENTATIVE OF DEVICE CLASS
64.86 µm
Peak Warpage
⚠ +29.7% vs Limit
1,960
Fatigue Cycles
⛔ −2% vs Target
0.18°C/W
Thermal Resistance
✓ Within Spec
4.2 ppm/°C
CTE Mismatch
▶ Acceptable
⚠ FINDING 01 · WARPAGE
Peak warpage 64.86 µm exceeds JEDEC limit (50 µm). Fix: Increase substrate core thickness.
⛔ FINDING 02 · FATIGUE
Predicted 1,960 cycles vs 2,000 floor. Corrective action required pre prototype.
04 //
The Opportunity
機會投遞
What I Bring
⬡
Full-Stack Packaging Depth
From substrate design to OSAT management (Tier-1 Accounts) and AI chiplet packaging.
◈
Rare Domain Convergence
Professional who runs high-fidelity physics models. Bridging engineering precision with market probability.
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